#ifndef _SCB_HW_H_
#define _SCB_HW_H_

#include "soc.h"

typedef struct {
	_OR CPUID;          /*!< Offset: 0x000 CPUID Base Register */
	_RW ICSR;           /*!< Offset: 0x004 Interrupt Control and State Register */
	_RW VTOR;           /*!< Offset: 0x008 Vector Table Offset Register */
	_RW AIRCR;          /*!< Offset: 0x00C Application Interrupt and Reset Control Register */
	_RW SCR;            /*!< Offset: 0x010 System Control Register */
	_RW CCR;            /*!< Offset: 0x014 Configuration Control Register */
	volatile uint8_t SHP[12U]; /*!< Offset: 0x018 System Handlers Priority Registers (4-7, 8-11, 12-15) */
	_RW SHCSR;          /*!< Offset: 0x024 System Handler Control and State Register */
	_RW CFSR;           /*!< Offset: 0x028 Configurable Fault Status Register */
	_RW HFSR;           /*!< Offset: 0x02C HardFault Status Register */
	_RW DFSR;           /*!< Offset: 0x030 Debug Fault Status Register */
	_RW MMFAR;          /*!< Offset: 0x034 MemManage Fault Address Register */
	_RW BFAR;           /*!< Offset: 0x038 BusFault Address Register */
	_RW AFSR;           /*!< Offset: 0x03C Auxiliary Fault Status Register */
	_OR PFR[2U];        /*!< Offset: 0x040 Processor Feature Register */
	_OR DFR;            /*!< Offset: 0x048 Debug Feature Register */
	_OR ADR;            /*!< Offset: 0x04C Auxiliary Feature Register */
	_OR MMFR[4U];       /*!< Offset: 0x050 Memory Model Feature Register */
	_OR ISAR[5U];       /*!< Offset: 0x060 Instruction Set Attributes Register */
	_NU RESERVED0[5U];
	_RW CPACR;          /*!< Offset: 0x088 Coprocessor Access Control Register */
} SCB_Struct;

extern SCB_Struct SOC_SCB;

/**
 * 中断和复位控制
 */
#define SCB_AIRCR_VECTRESET                  /* 保留调试器使用，写1后需要写0 */
#define SCB_AIRCR_VECTCLRACTIVE              /* 保留调试器使用，写1后需要写0 */
#define SCB_AIRCR_SYSRESETREQ_EN  (0x1U<<2)  /* 复位除调试器以外的其他模块 */
#define SCB_AIRCR_PRIGROUP_G16_S1 (0x3U<<8)  /* 中断分组，16组，无子优先级 */
#define SCB_AIRCR_PRIGROUP_G8_S2  (0x4U<<8)
#define SCB_AIRCR_PRIGROUP_G4_S4  (0x5U<<8)
#define SCB_AIRCR_PRIGROUP_G2_S8  (0x6U<<8)
#define SCB_AIRCR_PRIGROUP_G1_S16 (0x7U<<8)
#define SCB_AIRCR_ENDIANESS                  /* 固定0，小端模式 */
#define SCB_AIRCR_VECTKEY         (0x05FAU<<16) /* 写寄存器时需要写该值 */
/* 获取中断分组配置 */
#define _SCB_GetPriorityGroup(dev)  ((dev).AIRCR & (0x7U<<8))

/**
 * CP10 CP11协处理器使能，和浮点运算有关
 */
#define SCB_CPACR_DISABLE       (0x0U<<20)
#define SCB_CPACR_PRIVILEGED    (0x1U<<20)  /* 仅特权可访问 */
#define SCB_CPACR_FULL          (0x3U<<20)
#endif /* _SCB_HW_H_ */
